Block Structure Profiling in Three Dimensional Memory

ABSTRACT

Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes.

BACKGROUND

This application relates to the operation of re-programmable nonvolatilethree dimensional memory systems such as semiconductor flash memorywhich record data using charge stored in charge storage elements ofmemory cells.

Solid-state memory capable of nonvolatile storage of charge,particularly in the form of EEPROM and flash EEPROM packaged as a smallform factor card, has become the storage of choice in a variety ofmobile and handheld devices, notably information appliances and consumerelectronics products. Unlike RAM (random access memory) that is alsosolid-state memory, flash memory is non-volatile, and retains its storeddata even after power is turned off. Also, unlike ROM (read onlymemory), flash memory is rewritable similar to a disk storage device. Inspite of the higher cost, flash memory is increasingly being used inmass storage applications.

Flash EEPROM is similar to EEPROM (electrically erasable andprogrammable read-only memory) in that it is a non-volatile memory thatcan be erased and have new data written or “programmed” into theirmemory cells. Both utilize a floating (unconnected) conductive gate, ina field effect transistor structure, positioned over a channel region ina semiconductor substrate, between source and drain regions. A controlgate is then provided over the floating gate. The threshold voltagecharacteristic of the transistor is controlled by the amount of chargethat is retained on the floating gate. That is, for a given level ofcharge on the floating gate, there is a corresponding voltage(threshold) that must be applied to the control gate before thetransistor is turned “on” to penult conduction between its source anddrain regions. Flash memory such as Flash EEPROM allows entire blocks ofmemory cells to be erased at the same time.

The floating gate can hold a range of charges and therefore can beprogrammed to any threshold voltage level within a threshold voltagewindow. The size of the threshold voltage window is delimited by theminimum and maximum threshold levels of the device, which in turncorrespond to the range of the charges that can be programmed onto thefloating gate. The threshold window generally depends on the memorydevice's characteristics, operating conditions and history. Eachdistinct, resolvable threshold voltage level range within the windowmay, in principle, be used to designate a definite memory state of thecell.

Nonvolatile memory devices are also manufactured from memory cells witha dielectric layer for storing charge. Instead of the conductivefloating gate elements described earlier, a dielectric layer is used.Such memory devices utilizing dielectric storage element have beendescribed by Eitan et al., “NROM: A Novel Localized Trapping, 2-BitNonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11,November 2000, pp. 543-545. An ONO dielectric layer extends across thechannel between source and drain diffusions. The charge for one data bitis localized in the dielectric layer adjacent to the drain, and thecharge for the other data bit is localized in the dielectric layeradjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and6,011,725 disclose a nonvolatile memory cell having a trappingdielectric sandwiched between two silicon dioxide layers. Multi-statedata storage is implemented by separately reading the binary states ofthe spatially separated charge storage regions within the dielectric,

SUMMARY OF THE INVENTION

In some 3-D memory arrays, characteristics of a memory cell may dependon the diameter of a memory hole where it intersects the memory cell.Memory holes may be non-uniform along their length, and different memoryholes may have different profiles. Memory hole diameter may becalculated from characteristics that are observed during programming.Knowing a memory hole profile of a block allows suitable operatingparameters to be selected for operating the block. Memory hole profileof a plane may be used to select operating parameters for the plane.Memory hole profile of a die may be used to select operating parametersfor the die. Smaller memory holes result in earlier failure. Hot countsmay be adjusted according to memory hole size so that blocks that areexpected to fail earlier because of small memory holes are more lightlyused than blocks with larger memory holes.

An example of a method of characterizing a three-dimensional NAND memorydie includes: selecting a plurality of sample blocks from thethree-dimensional NAND memory array; writing sample data to a pluralityof sample word lines of a plurality of physical levels of the sampleblocks to obtain characterization information for the sample word lines;and calculating a physical dimension of memory cells at each of theplurality of levels from the characterization information.

The sample data may consist of a predetermined test pattern forefficiently obtaining the characterization information. The test patternmay assign first logic states to memory cells on a drain side of a NANDstring and assign second logic states that are the inverse of thecorresponding first logic states to corresponding memory cells on thesource side of the NAND string. The physical dimension may be a diameterof a vertical memory hole that extends through memory cells in each ofthe plurality of levels. The physical dimension may be a thickness of alayer formed in a memory hole that extends through memory cells in eachof the plurality of levels. The three-dimensional NAND memory die mayinclude a plurality of planes, and selecting the plurality of sampleblocks may include selecting at least one sample block from each of theplurality of planes. The plurality of sample word lines of the pluralityof physical levels may include at least one word line from each level inthe three-dimensional NAND memory die. The plurality of sample wordlines may include all word lines of a sample block. The method mayinclude recording the physical dimension in the three-dimensional NANDmemory die. Operating parameters may be selected for memory cells ateach of the plurality of levels based on the calculated physicaldimension of memory cells at each of the plurality of levels. Theoperating parameters may include programming voltage and/or programmingtime used during a write operation. The selected operating parametersmay be recorded for each of the plurality of levels. Parameter updatingschemes may be selected for the selected operating parameters based onthe calculated physical dimension of the memory cells at each of theplurality of levels. A first parameter updating scheme may updateparameters associated with small memory hole diameter at a first rateand a second parameter updating scheme may update parameters associatedwith large memory hole diameter at a second rate that is different tothe first rate. The first parameter updating scheme may update a wearlevel indicator associated with small memory hole diameter at the firstrate and the second parameter updating scheme may update a wear levelindicator associated with large memory hole diameter at a second ratethat is slower than the first rate.

An example of a method of characterizing a three-dimensional NAND memorydie includes: selecting a plurality of sample blocks from thethree-dimensional NAND memory array; writing sample data to a pluralityof sample word lines in a sample block, each physical level in a sampleblock containing at least one of the plurality of sample word lines, toobtain characterization information for the sample word lines; andcalculating a memory hole diameter at each physical level in the sampleblock from the characterization information.

The write characterization information may include loop countinformation for programming the sample word lines. The writecharacterization information may include information obtained fromverification when programming the sample word lines. The writecharacterization information may include maximum programming voltageinformation for programming the sample word lines. A wear rate may becalculated for each level from the calculated memory hole diameter forthe level. A wear rate for a particular level may indicate the rate atwhich memory cells of the level approach a wear-out condition withincreasing numbers of write-erase cycles.

An example of a three-dimensional NAND memory includes: an array ofmemory cells arranged in a plurality of levels; a plurality of memoryhole structures extending vertically through the plurality of levels toconnect memory cells of the plurality of levels in NAND strings; a writecircuit configured to write sample data to sample word lines atdifferent levels of the plurality of levels; and a characterizationcircuit configured to receive information regarding the writing ofsample data to sample word lines from the write circuit, thecharacterization circuit determining one or more physical dimensions ofa memory hole structure at the different levels from the information.

Read circuits may be configured to read the sample data from the sampleword lines at different levels of the plurality of levels and to sendinformation regarding the reading of sample data to the characterizationcircuit. The information regarding the reading of sample data may beused to determine the one or more physical dimensions. The one or morephysical dimensions may include an outer dimension of the memory holestructure established by an inner dimension of a memory hole in whichthe memory hole structure is formed. The information regarding thewriting of sample data to sample word lines may include at least one of:loop count information, verification information, and maximumprogramming voltage information for each of the sample word lines.

An example of a method of operating a three-dimensional NAND memory dieincludes: testing memory cells at a plurality of levels in thethree-dimensional NAND memory array to obtain characterizationinformation for each of the plurality of levels; calculating a physicaldimension of memory cells at each of the plurality of levels from thecharacterization information; calculating at least one initial value ofan operating parameter for each of the plurality of levels, the initialvalue of the operating parameter for a level calculated from thephysical dimension calculated for the level; and calculating a rate ofchange of the operating parameter for each of the plurality of levels,the rate of change of the operating parameter for a level calculatedfrom the physical dimension calculated for the level.

The physical dimension may be a diameter of a memory hole that extendsthrough memory cells. A higher rate of change of the operating parametermay be calculated for smaller memory hole diameter and a lower rate ofchange of the operating parameter is calculated for larger memory holediameter. After a period of use, testing of the memory cells may berepeated at the plurality of levels in the three-dimensional NAND memoryarray to obtain post-use characterization information. The post-usecharacterization information may be compared with the characterizationinformation and recalculating the physical dimension of memory cells ateach of the plurality of levels from the post-use characterizationinformation if a difference between the post use characterizationinformation and the characterization information exceeds a thresholdamount. An aggregated memory hole diameter may be calculated for a blockand a wear rate may be calculated for the block from the aggregatedmemory hole diameter. An effective age for the block may be calculatedfrom the number of write-erase cycles experienced by the block and thewear rate calculated for the block.

Various aspects, advantages, features and embodiments of the presentinvention are included in the following description of exemplaryexamples thereof, which description should be taken in conjunction withthe accompanying drawings. All patents, patent applications, articles,other publications, documents and things referenced herein are herebyincorporated herein by this reference in their entirety for allpurposes. To the extent of any inconsistency or conflict in thedefinition or use of terms between any of the incorporated publications,documents or things and the present application, those of the presentapplication shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically the main hardware components of amemory system suitable for implementing the present invention.

FIG. 2 illustrates schematically a non-volatile memory cell.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that the floating gate may be selectively storing at any one time atfixed drain voltage.

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel.

FIGS. 6A-6C illustrate an example of programming a population of memorycells.

FIG. 7 shows an example of a physical structure of a 3-D NAND string.

FIG. 8 shows an example of a physical structure of a U-shaped 3-D NANDstring.

FIG. 9A shows a cross section of a 3-D NAND memory array in the y-zplane.

FIG. 9B shows a cross section of the 3-D NAND memory array of FIG. 9Aalong the x-y plane.

FIGS. 10A-10B shows examples of structures of NAND strings.

FIG. 11 is a schematic of a NAND string with two wings connected by aback gate.

FIG. 12A shows variation in memory hole diameter.

FIG. 12B shows a cross section of a memory hole in an upper level.

FIG. 12C shows a cross section of a memory hole in a lower level.

FIG. 13 illustrates a series of program pulses with verify steps.

FIG. 14 illustrates a memory characterization operation.

FIG. 15 shows an example of a memory system with adaptive erase.

DETAILED DESCRIPTION Memory System

FIG. 1 illustrates schematically the main hardware components of amemory system suitable for implementing the present invention. Thememory system 90 typically operates with a host 80 through a hostinterface. The memory system may be in the form of a removable memorysuch as a memory card, or may be in the form of an embedded memorysystem. The memory system 90 includes a memory 102 whose operations arecontrolled by a controller 100. The memory 102 comprises one or morearray of non-volatile memory cells distributed over one or moreintegrated circuit chip. The controller 100 may include interfacecircuits 110, a processor 120, ROM (read-only-memory) 122, RAM (randomaccess memory) 130, programmable nonvolatile memory 124, and additionalcomponents. The controller is typically formed as an ASIC (applicationspecific integrated circuit) and the components included in such an ASICgenerally depend on the particular application.

Physical Memory Structure

FIG. 2 illustrates schematically a non-volatile memory cell. The memorycell 10 can be implemented by a field-effect transistor having a chargestorage unit 20, such as a floating gate or a charge trapping(dielectric) layer. The memory cell 10 also includes a source 14, adrain 16, and a control gate 30.

There are many commercially successful non-volatile solid-state memorydevices being used today. These memory devices may employ differenttypes of memory cells, each type having one or more charge storageelement.

Typical non-volatile memory cells include EEPROM and flash EEPROM.Examples of EEPROM cells and methods of manufacturing them are given inU.S. Pat. No. 5,595,924. Examples of flash EEPROM cells, their uses inmemory systems and methods of manufacturing them are given in U.S. Pat.Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421and 6,222,762. In particular, examples of memory devices with NAND cellstructures are described in U.S. Pat. Nos. 5,570,315, 5,903,495,6,046,935. Also, examples of memory devices utilizing dielectric storageelements have been described by Eitan et al., “NROM: A Novel LocalizedTrapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters,vol. 21, no. 11, November 2000, pp. 543-545, and in U.S. Pat. Nos.5,768,192 and 6,011,725.

In practice, the memory state of a cell is usually read by sensing theconduction current across the source and drain electrodes of the cellwhen a reference voltage is applied to the control gate. Thus, for eachgiven charge on the floating gate of a cell, a corresponding conductioncurrent with respect to a fixed reference control gate voltage may bedetected. Similarly, the range of charge programmable onto the floatinggate defines a corresponding threshold voltage window or a correspondingconduction current window.

Alternatively, instead of detecting the conduction current among apartitioned current window, it is possible to set the threshold voltagefor a given memory state under test at the control gate and detect ifthe conduction current is lower or higher than a threshold current(cell-read reference current). In one implementation the detection ofthe conduction current relative to a threshold current is accomplishedby examining the rate the conduction current is discharging through thecapacitance of the bit line.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that the floating gate may be selectively storing at any one time. Withfixed drain voltage bias, the four solid I_(D) versus V_(CG) curvesrepresent four of seven possible charge levels that can be programmed ona floating gate of a memory cell, respectively corresponding to fourpossible memory states. As an example, the threshold voltage window of apopulation of cells may range from 0.5V to 3.5V. Seven possibleprogrammed memory states “0”, “1”, “2”, “3”, “4”, “5”, “6”, and anerased state (not shown) may be demarcated by partitioning the thresholdwindow into regions in intervals of 0.5V each. For example, if areference current, IREF of 2 μA is used as shown, then the cellprogrammed with Q1 may be considered to be in a memory state “1” sinceits curve intersects with I_(REF) in the region of the threshold windowdemarcated by VCG=0.5V and 1.0V. Similarly, Q4 is in a memory state “5”.

As can be seen from the description above, the more states a memory cellis made to store, the more finely divided is its threshold voltagewindow. For example, a memory device may have memory cells having athreshold voltage window that ranges from −1.5V to 5V. This provides amaximum width of 6.5V. If the memory cell is to store 16 states, eachstate may occupy from 200 mV to 300 mV in the threshold window. Thiswill require higher precision in programming and reading operations inorder to be able to achieve the required resolution.

NAND Structure

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string. A NAND string 50 comprises a series of memorytransistors M1, M2, . . . Mn (e.g., n=4, 8, 16 or higher) daisy-chainedby their sources and drains. A pair of select transistors S1, S2controls the memory transistor chain's connection to the external worldvia the NAND string's source terminal 54 and drain terminal 56respectively. In a memory array, when the source select transistor S1 isturned on, the source terminal is coupled to a source line (see FIG.4B). Similarly, when the drain select transistor S2 is turned on, thedrain terminal of the NAND string is coupled to a bit line of the memoryarray. Each memory transistor 10 in the chain acts as a memory cell. Ithas a charge storage element 20 to store a given amount of charge so asto represent an intended memory state. A control gate 30 of each memorytransistor allows control over read and write operations. As will beseen in FIG. 4B, the control gates 30 of corresponding memorytransistors of a row of NAND string are all connected to the same wordline. Similarly, a control gate 32 of each of the select transistors S1,S2 provides control access to the NAND string via its source terminal 54and drain terminal 56 respectively. Likewise, the control gates 32 ofcorresponding select transistors of a row of NAND string are allconnected to the same select line.

When an addressed memory transistor 10 within a NAND string is read oris verified during programming, its control gate 30 is supplied with anappropriate voltage. At the same time, the rest of the non-addressedmemory transistors in the NAND string 50 are fully turned on byapplication of sufficient voltage on their control gates. In this way, aconductive path is effectively created from the source of the individualmemory transistor to the source terminal 54 of the NAND string andlikewise for the drain of the individual memory transistor to the drainterminal 56 of the cell. Memory devices with such NAND string structuresare described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A. Alongeach column of NAND strings, a bit line such as bit line 36 is coupledto the drain terminal 56 of each NAND string. Along each bank of NANDstrings, a source line such as source line 34 is coupled to the sourceterminals 54 of each NAND string. Also the control gates along a row ofmemory cells in a bank of NAND strings are connected to a word line suchas word line 42. The control gates along a row of select transistors ina bank of NAND strings are connected to a select line such as selectline 44. An entire row of memory cells in a bank of NAND strings can beaddressed by appropriate voltages on the word lines and select lines ofthe bank of NAND strings.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel. FIG. 5essentially shows a bank of NAND strings 50 in the memory array 210 ofFIG. 4B, where the detail of each NAND string is shown explicitly as inFIG. 4A. A physical page, such as the page 60, is a group of memorycells enabled to be sensed or programmed in parallel. This isaccomplished by a corresponding page of sense amplifiers 212. The sensedresults are latched in a corresponding set of latches 214. Each senseamplifier can be coupled to a NAND string via a bit line. The page isenabled by the control gates of the cells of the page connected incommon to a word line 42 and each cell accessible by a sense amplifieraccessible via a bit line 36. As an example, when respectively sensingor programming the page of cells 60, a sensing voltage or a programmingvoltage is respectively applied to the common word line WL3 togetherwith appropriate voltages on the bit lines.

Physical Organization of the Memory

One important difference between flash memory and other of types ofmemory is that a cell must be programmed from the erased state. That isthe floating gate must first be emptied of charge. Programming then addsa desired amount of charge back to the floating gate. It does notsupport removing a portion of the charge from the floating gate to gofrom a more programmed state to a lesser one. This means that updateddata cannot overwrite existing data and must be written to a previousunwritten location.

Furthermore erasing is to empty all the charges from the floating gateand generally takes appreciable time. For that reason, it will becumbersome and very slow to erase cell by cell or even page by page. Inpractice, the array of memory cells is divided into a large number ofblocks of memory cells. As is common for flash EEPROM systems, the blockis the unit of erase. That is, each block contains the minimum number ofmemory cells that are erased together. While aggregating a large numberof cells in a block to be erased in parallel will improve eraseperformance, a large size block also entails dealing with a largernumber of update and obsolete data.

Each block is typically divided into a number of physical pages. Alogical page is a unit of programming or reading that contains a numberof bits equal to the number of cells in a physical page. In a memorythat stores one bit per cell, one physical page stores one logical pageof data. In memories that store two bits per cell, a physical pagestores two logical pages. The number of logical pages stored in aphysical page thus reflects the number of bits stored per cell. In oneembodiment, the individual pages may be divided into segments and thesegments may contain the fewest number of cells that are written at onetime as a basic programming operation. One or more logical pages of dataare typically stored in one row of memory cells. A page can store one ormore sectors. A sector includes user data and overhead data.

All-bit Full-Sequence MLC Programming

FIG. 6A-6C illustrate an example of programming a population of 4-statememory cells. FIG. 6A illustrates the population of memory cellsprogrammable into four distinct distributions of threshold voltagesrespectively representing memory states “E”, “A”, “B” and “C”. FIG. 6Billustrates the initial distribution of “erased” threshold voltages foran erased memory. FIG. 6C illustrates an example of the memory aftermany of the memory cells have been programmed. Essentially, a cellinitially has an “erased” threshold voltage and programming will move itto a higher value into one of the three zones demarcated by verifylevels vV₁, vV₂ and vV₃. In this way, each memory cell can be programmedto one of the three programmed states “A”, “B” and “C” or remainun-programmed in the “erased” state. As the memory gets moreprogramming, the initial distribution of the “erased” state as shown inFIG. 6B will become narrower and the erased state is represented by the“0” state.

A 2-bit code having a lower bit and an upper bit can be used torepresent each of the four memory states. For example, the “E”, “A”, “B”and “C” states are respectively represented by “11”, “01”, “00” and‘10”. The 2-bit data may be read from the memory by sensing in“full-sequence” mode where the two bits are sensed together by sensingrelative to the read demarcation threshold values rV₁, rV₂ and rV₃ inthree sub-passes respectively.

3-D NAND Structure

An alternative arrangement to a conventional two-dimensional (2-D) NANDarray is a three-dimensional (3-D) array. In contrast to 2-D NANDarrays, which are formed along a planar surface of a semiconductorwafer, 3-D arrays extend up from the wafer surface and generally includestacks, or columns, of memory cells extending upwards. Various 3-Darrangements are possible. In one arrangement a NAND string is formedvertically with one end (e.g. source) at the wafer surface and the otherend (e.g. drain) on top. In another arrangement a NAND string is formedin a U-shape so that both ends of the NAND string are accessible on top,thus facilitating connections between such strings. Examples of suchNAND strings and their formation are described in U.S. PatentPublication Number 2012/0220088 and in U.S. Patent Publication Number2013/0107628, which are hereby incorporated by reference in theirentirety.

FIG. 7 shows a first example of a NAND string 701 that extends in avertical direction, i.e. extending in the z-direction, perpendicular tothe x-y plane of the substrate. Memory cells are formed where a verticalbit line (local bit line) 703 passes through a word line (e.g. WL0, WL1,etc.). A charge trapping layer between the local bit line and the wordline stores charge, which affects the threshold voltage of thetransistor formed by the word line (gate) coupled to the vertical bitline (channel) that it encircles. Such memory cells may be fanned byforming stacks of word lines and then etching memory holes where memorycells are to be formed. Memory holes are then lined with a chargetrapping layer and filled with a suitable local bit line/channelmaterial (with suitable dielectric layers for isolation).

As with planar NAND strings, select gates 705, 707, are located ateither end of the string to allow the NAND string to be selectivelyconnected to, or isolated from, external elements 709, 711. Suchexternal elements are generally conductive lines such as common sourcelines or bit lines that serve large numbers of NAND strings. VerticalNAND strings may be operated in a similar manner to planar NAND stringsand both SLC and MLC operation is possible. While FIG. 7 shows anexample of a NAND string that has 32 cells (0-31) connected in series,the number of cells in a NAND string may be any suitable number. Not allcells are shown for clarity. It will be understood that additional cellsare formed where word lines 3-29 (not shown) intersect the localvertical bit line.

FIG. 8 shows a second example of a NAND string 815 that extends in avertical direction (z-direction). In this case, NAND string 815 forms aU-shape, connecting with external elements (source line “SL” and bitline “BL”) located on the top of the structure. At the bottom of NANDstring 815 is a controllable gate (back gate “BG”) which connects thetwo wings 816A, 816B of NAND string 815. A total of 64 cells are formedwhere word lines WL0-WL63 intersect the vertical local bit line 817(though in other examples other numbers of cells may be provided).Select gates SGS, SGD, are located at either end of NAND string 815 tocontrol connection/isolation of NAND string 815.

Vertical NAND strings may be arranged to form a 3-D NAND array invarious ways. FIG. 9A shows an example where multiple U-shaped NANDstrings in a block are connected to a bit line. In this case, there aren strings (Sting 1-String n) in a block connected to a bit line (“BL”).The value of “n” may be any suitable number, for example, 8, 12, 16, 32,or more. Strings alternate in orientation with odd numbered stringshaving their source connection on the left, and even numbered stringshaving their source on the right. This arrangement is convenient but isnot essential and other patterns are also possible.

FIG. 9A shows where two blocks meet. Block A contains n stringsconnected to the bit line BL. While only strings n, and n−1 of Block Aare shown, it will be understood that the repetitive structure continuesto the left where strings 1 to n−2 are located. Block B contains nstrings connected to bit line BL. While only strings 1-3 of Block B areshown, it will be understood that the repetitive structure continues tothe right where strings 4 to n are located. It will also be understoodthat the cross section shown is along one of many bit lines that servethe block and that there are many similar bit lines extending along they-direction, separated from each other in the x-direction (e.g. behindthe plane of the cross section shown). Word lines extend in thex-direction, perpendicular to the plane of FIG. 9A, to connect sets ofstrings of different bit lines. Similarly, select lines extend in thex-direction so that a set of strings may be selectively connected, orisolated, as a unit. In the example shown, word lines are formed so thata single conductive strip forms a word line of two adjacent strings.Thus, for example, in Block B, string 1 and string 2 have word linesWL32-WL63 that are formed by common conductive strips. In contrast,select lines are not shared between neighboring strings. This allowsseparate selection of an individual set of strings within a block, eventhough the selected set of strings may include word lines that are notseparately controllable from word lines of unselected strings.

FIG. 9A shows dummy word lines “DWL” separating select lines SGD, SGS,from host data word lines WL0-WL63. While host data word lines are usedto store host data (i.e. data that may be sent to the memory from anexternal source with the expectation that the data will be returned inresponse to a read command), dummy word lines do not store host data.They may store nothing, or may store some dummy data that puts the dummycells in a desirable condition (e.g. puts their threshold voltages atlevels that make accessing other cells easier, or reduces risk ofdisturbance). The dummy word lines shown provide some protection forstored data.

Each block has a separate back gate, BG, so that back gate transistorsof different blocks may be separately controlled. Back gates extend inthe x-direction, perpendicular to the cross section of FIG. 9A, so thatall back gate transistors of a block are controlled by a common backgate in this example. Control circuits are connected to the back gatesof each block so that appropriate bias may be applied to back gates. Thestructure of back gates is further explained below.

Common source lines “SL” connect to one end of each NAND string(opposite to the end that connects to the bit line). This may beconsidered the source end of the NAND string, with the bit line endbeing considered as the drain end of the NAND string. Common sourcelines may be connected so that all source lines for a block may becontrolled together by a peripheral circuit. Thus, NAND strings of ablock extend in parallel between bit lines on one end, and common sourcelines on the other end.

The 3-D NAND memory array of FIG. 9A is further illustrated in FIG. 9B,which shows a cross section along A-A′ of FIG. 9A (i.e. along the x-yplane that intersects WL0 and WL63). It can be seen that word lines of ablock are formed of strips of conductive material that are connectedtogether. Thus, all word lines marked WL0 in different strings of ablock are electrically connected together and are formed from a singleelectrically conductive body 921. Similarly, all word lines marked WL63in different strings of a block are electrically connected together andare formed from a single electrically conductive body 923. The twobodies that form word lines of a block on a given level appear asinterdigitated fingers extending from opposite sides of the block. Thesetwo bodies may be separated by Shallow Trench Isolation (STI)dielectric, or by any suitable insulator. A similar pattern may be foundat each level of word lines (e.g. WL1 and WL62 are similarlyinterdigitated, as are WL2 and WL61, and so on). Word lines of differentblocks are isolated from each other. Thus, WL0 of Block A is separate,and electrically isolated from WL0 of Block B. Similarly, WL63 of BlockA is separate, and electrically isolated from WL63 of Block B.

Memory holes are shown as circles (memory holes are cylindrical in shapeand extend in the z-direction, perpendicular to the cross sectionshown). A U-shaped NAND string 925 extends along two memory holes 927,929, with one memory hole 927 passing through body 923 and the othermemory hole 929 passing through body 921. A set of strings consists ofall such strings that are aligned along the x-direction and that shareselect lines (which also extend along the x-direction). For example, onesuch set is made up of all strings indicated by “String 3” in Block B,including string 925.

FIG. 10A shows a cross section along a y-z plane that intersects memoryholes 927, and 929 of NAND string 925 so that the structures formedwithin memory holes (memory hole structures) may be clearly seen. FIG.10A shows that memory holes 927 and 929 are connected together at thebottom so that the two wings may be electrically connected in series.

FIG. 10B shows the structure of a stack of layers in the memory hole 929where memory cells are formed (the memory hole structure). It can beseen that a blocking dielectric “Block” 181 is deposited on the walls ofthe memory hole to provide electrical isolation from word lines 180 a,180 b. A Charge Trapping Layer (CTL) 183 is deposited on the blockingdielectric 181. The CTL layer 183 forms charge storage elements wherethe CTL is in close proximity to polysilicon word lines 180 a, 180 b. Atunnel dielectric 185 is deposited to provide electrical isolation andto allow charge to tunnel into the CTL layer 183 under certainconditions. A channel layer 187 is deposited to form the channel of thememory cells along the string. A core material 189 is deposited thatforms the core of the column that is located in the memory hole.

FIG. 11 shows a schematic of a U-shaped NAND string, similar to theU-shaped NAND strings of FIG. 10A, including memory cells M0-M63. Inorder to access the cells of the NAND string, appropriate voltages areapplied to various lines associated with the NAND string, including thesource select line, drain select line, source line, and bit line.Programming, reading, and erasing of memory cells may be performed byapplying appropriate voltages using driver circuits in a peripheral areaof a memory chip.

One difference between a three dimensional memory array and a twodimensional memory array is that certain physical dimensions of memorycells may vary with the location of the memory cells in the verticaldirection. While memory cells in a planar array may be made by processsteps that generally have uniform effect across the plane of thesubstrate, some steps in formation of three dimensional memory arraysare not uniform from layer to layer and may also have significantnon-uniformity laterally across a substrate. For example, memory holesmay be formed by etching down through multiple layers using anappropriate anisotropic etch. However, such holes may not be perfectlyuniform from top to bottom because of the high aspect ratio that istypical of such memory holes. In general, such memory holes are widertowards the top than the bottom. Or, they may be widest somewhere nearthe top with some narrowing towards the top.

FIG. 12A shows an example of how memory hole diameter may vary withvertical distance from the substrate. Memory holes are narrower towardsthe bottom of the memory hole compared with the top of the memory hole.FIG. 12B shows a cross section of a memory hole having a relativelylarge diameter, d1, for example near the top of a memory hole(relatively far from the substrate). FIG. 12C shows a cross section of amemory hole having a relatively small diameter, d2, for example near thebottom of a memory hole (relatively near the substrate). Diameter d2 issignificantly less than diameter d1 which leads to a significantlystronger electric field within the memory hole of FIG. 12C compared withFIG. 12B under the same conditions (e.g. when the same voltage appliedto the word line). A higher electric field affects the characteristicsof memory cells. For example, programming and erase may be faster for asmaller diameter memory hole under the same conditions. Higher electricfield strength may also cause increased wear and earlier failure ofmemory cells with small memory hole diameters.

Knowledge of memory hole diameters at different locations may allowmemory operation at those locations to be adapted according to theexpected characteristics. U.S. patent application Ser. No. 13/791,200,filed on Mar. 8, 2013, entitled, “Optimized configurable NANDparameters,” and corresponding U.S. Provisional Application No.61/731,198, filed on Nov. 29, 2012, which are hereby incorporated byreference in their entirety, describe predicted memory hole variationand how it may be used to select appropriate parameters for differentlevels. U.S. patent application Ser. No. 13/801,741, filed on Mar. 13,2013, entitled, “Weighted read scrub for nonvolatile memory,” andcorresponding Provisional Application No. 61/731,215, filed on Nov. 29,2012, which are hereby incorporated by reference in their entirety,describe prioritizing scrubbing of data according to predicted memoryhole size.

Memory hole diameter as a function of location is somewhat predictablebecause etch chemistry tends to produce larger diameters near the top ofan etched memory hole than near the bottom. However, this predictabilityis limited and there may be significant variation from one memory holeto another. Different dies formed in the same wafer may have memoryholes with different profiles. For example, dies near the edge of awafer may have different memory hole profiles than dies near the centerof a wafer. Even within a single die, there may be significant variationfrom block to block.

According to an aspect of the present invention, memory hole diametersat different locations are determined by performing certaincharacterization operations from which the diameters of memory holes arecalculated. Thus, memory hole diameters are found by direct testingrather than being assumed from some model, or from some testing on asample chip. This allows a memory hole profile to be calculated fromcharacterization information for an individual block, plane, die, orother unit. Such specific knowledge of memory hole profiles may allowmore accurate use of techniques based on memory hole profiles such asoptimizing parameters, weighted scrub, or other techniques. For example,a wear leveling scheme may be configured to ensure that memory cellswith smaller memory holes that tend to wear faster receive fewerwrite/erase cycles than memory holes with larger memory holes that tendto wear more slowly.

In an example, memory hole profiles of a memory die are obtained byperforming characterization operations on sample blocks in the die. Thischaracterization may be performed as part of a testing operation at afactory (e.g. combined with looking for bad blocks, bad word lines,physical defects, etc.). Alternatively, memory hole characterization maybe performed after a memory die has left the factory, after it isincorporated into a memory system. A memory controller that is connectedto the memory die may perform the characterization operation. Such acontroller may be configured by firmware to carry out thecharacterization operation and to use the characterization informationobtained to operate the memory die in an efficient manner.

Characterization operations to determine memory hole diameter mayinclude a number of different steps. Program, data retention, read, anderase characteristics may vary according to memory hole diameter so thatprogram, retention, read, and/or erase steps may be used to obtaincharacterization information. A combination of such steps may providemore accurate information.

While memory hole diameter is one physical dimension that may beobtained, aspects of the present invention may be used to obtain otherphysical dimensions of memory cells also. For example, thicknesses ofdifferent layers in a memory hole structure may vary with location(layers may be thinner near the bottom of a memory hole compared withnear the top). For example, tunnel dielectric layer thickness may varyand may affect memory cell characteristics. Program, read, and eraseoperations may be affected by such dimensions. Characterizationinformation may be used to calculate such thicknesses. For example,tunnel dielectric thickness, blocking dielectric thickness, or otherlayer thicknesses, may be obtained from characterization information.

According to an example, characterization information may be obtainedfrom programming test data to memory cells and observing the time and/orvoltages needed to bring memory cells along a word line to theirprogrammed states. Programming of flash memory cells along a word linegenerally includes applying a series of programming pulses to the wordline, with appropriate voltages on channels to promote or inhibit chargeflow to charge storage elements. In some systems, the number ofprogramming pulses needed to program a word line and/or otherprogramming parameters may be recorded and used as characterizationinformation. U.S. patent application Ser. No. 13/940,504, filed on Jun.12, 2013, entitled, “Efficient smart verify method for programming 3Dnon-volatile memory,” and corresponding U.S. Provisional Application No.61/763,085, filed on Feb. 11, 2013, which are hereby incorporated byreference in their entirety, describe using the number of programmingpulses (loop count) for an initial set of memory cells to determine anappropriate programming voltages for subsequent memory cells. U.S.patent application Ser. No. 14/025,160, filed on Sep. 12, 2013,entitled, “Vread bias allocation on word lines for read disturbreduction in 3D non-volatile memory,” which is hereby incorporated byreference in its entirety, describes calculating read pass voltagesbased on program voltage trim values.

FIG. 13 illustrates a technique for programming a 4-state memory cell toa target memory state. Programming circuits generally apply a series ofprogramming pulses to a selected word line. In this way, a page ofmemory cells whose control gates are coupled to the word line can beprogrammed together. The programming pulse train used may haveincreasing period or amplitude in order to counteract the accumulatingelectrons programmed into the charge storage unit of the memory cell. Aprogramming voltage V_(PGM) is applied to the word line of a page underprogramming. The programming voltage V_(PGM) is a series of programmingvoltage pulses in the form of a staircase waveform starting from aninitial voltage level, V_(PGM0), then V_(PGM1), then V_(PGM2), and soon. Each cell of the page under programming is subject to this series ofprogramming voltage pulses, with an attempt at each pulse to addincremental charges to the charge storage element of the cell. Inbetween programming pulses, the cell is read back to determine itsthreshold voltage. The read back process may involve one or more sensingoperation. Programming stops for the cell when its threshold voltage hasbeen verified to fall within the threshold voltage zone corresponding tothe target state. Whenever a memory cell of the page has been programmedto its target state, it is program-inhibited while the other cellscontinue to be subject to programming until all cells of the page havebeen program-verified. One method of program-inhibiting a memory cell isto raise its bit line voltage from 0V to VCC during programming. In thisway, even when the cell's control gate has a programming voltage on it,the effective programming voltage on the floating gate is reduced byVCC, thereby inhibiting further programming of the cell.

During programming, characterization information may be recorded forlater use. For example, when programming along a particular word line,the number of programming pulses needed to complete programming (loopcount) may be recorded for the word line. Loop count may vary from wordline to word line. In particular, loop count is generally smaller formemory cells with small memory holes and larger for memory cells withlarge memory holes because of the stronger electric field created in asmaller memory hole under the same applied voltages.

In some cases the highest program voltage used may be recorded ascharacterization information. For example, if programming of a word lineends after a pulse of VPGM3 is applied then VPGM3 may be recorded as thehighest programming voltage used. In general, higher voltage pulses areneeded for larger memory holes. After data is programmed, the data maybe maintained in the memory cells over a period of time to test dataretention characteristics of the memory cells. Environmental factors maybe controlled during this period to simulate real world conditions orworst case scenarios. For example, temperature may be raised above roomtemperature, electromagnetic fields may be applied, mechanical vibrationor shock may be applied, or other environmental parameters may becontrolled in various ways. The memory array may be accessed during dataretention testing, for example by writing and erasing other portions ofthe memory array and by read operations directed to the test pattern orto other data. Data may then be read and additional characterizationinformation may be collected during reading. Characterizationinformation may also be collected from erase operations although suchinformation may be on a block by block basis rather than a word line byword line basis.

Characterization information gathered from one or more test operationsmay be used to calculate memory hole diameter. In general,characterization information may be correlated to memory hole diametereither using actual memory hole diameters obtained from destructivetesting of sample dies, or using modeling. For example, testing may showthat memory hole diameter of X nanometers correlates with a loopcount=Y. Once such a correlation is obtained from destructive testing ofsample dies, it may be used to calculate memory hole diameter inoperational dies from non-destructive testing.

While level to level variation in memory hole diameter is somewhatpredictable for a given process (i.e. for a given stack of layers to beetched, etch chemistry, nominal memory hole diameter and depth),variation from one memory hole to another across a wafer, or within adie may be less predictable. Knowledge of such variation may allowdifferent dies to be operated using operating parameters that are bettersuited to their particular physical structures. Even within a die,different planes, or different blocks may have different memory holeprofiles that affect performance. Knowledge of such profile variationmay allow the memory system to select appropriate operating parameterson a plane by plane or block by block basis.

According to an aspect of the present invention, sample blocks areselected in a memory die for memory hole characterization. It may bedesirable to select at least one block from each plane in the memorydie. In some cases memory hole characterization is performed on allblocks (i.e. all blocks are sample blocks). A test pattern is programmedto memory cells of the sample blocks and characterization information iscollected. The characterization information is then correlated withmemory hole diameter and an average memory hole profile, or someaggregated memory hole data, may be generated for each sample block.Operating parameters may be selected based on the aggregated memory holedata. For example, operating parameters for a plane may be selectedbased on the average memory hole profile obtained for a sample block orblocks in the plane. In some cases, a single average memory hole profileis obtained for an entire die.

A suitable test pattern may be selected to efficiently obtain thedesired characterization data. A test pattern may program all word linesof a block, or a subset of all word lines. In some cases, a test patternmay represent a worst case scenario (e.g. with a large number of memorycells programmed to high states). In some cases, a test pattern may bedesigned to quantify the effect of earlier programmed cells on laterprogrammed cells along NAND strings (sometimes referred to as a “backpattern effect”). In one example, a pattern of data is programmed alongU-shaped NAND strings so that the data pattern on the source side is theinverse of the data pattern on the drain side. This ensures that eachcell has a different memory state to a corresponding memory cell in thesame NAND string that is at the same level.

Block Aging

According to an example, a memory hole profile, and/or other aggregateddata, is calculated for each block and is used to determine operatingparameters for the block. Knowledge of memory hole profiles allows someblock-specific prediction of aging characteristics. Blocks with narrowermemory holes may be expected to wear faster. That is, because of thehigher electric field in such a block, the block would be expected towear out after a smaller number of write-erase cycles. Life expectancyof a block increases with memory hole diameter so knowing memory holediameter allows prediction of life expectancy of the block. An averagememory hole diameter for the block may be used for this purpose, or aweighted average, or the smallest memory hole diameter of the block maybe used. Some memory systems track the number of write-erase cycles foreach block (“hot count”) and use these numbers to perform wear levelingso that blocks experience similar usage and so that blocks do not tendto wear out prematurely. These numbers may be adjusted to reflect lifeexpectancy so that usage is more concentrated in blocks with longer lifeexpectancy, and blocks with low life expectancy experience lighterusage.

According to an example, fixed values are added to hot counts of blocksthat have narrow memory holes. For example, a block may have its hotcount incremented by 100 for every nanometer by which its memory holediameter is less than a nominal memory hole diameter. Thus, a block witha memory hole diameter that is 3 nm less than the nominal memory holediameter would have its hot count incremented by 300 and wear levelingwould direct new writes to other blocks until hot counts of other blocksreached 300 cycles.

According to another example, individualized multipliers are applied tothe actual hot counts of different blocks. Thus, while some blocks mayhave hot counts incremented by one for each write-erase cycle, otherblocks may apply a multiplier X so that their hot count increases by Xfor each write-erase cycle. The value of X may be a function of thedifference between actual memory hole diameter and a nominal memory holediameter. For example, the multiplier may be the number of nanometers bywhich a block's memory hole diameter is less than a nominal memory holediameter. Thus, a block with a memory hole diameter that is 3 nm lessthan the nominal memory hole diameter would have its hot count increaseby three every time it undergoes a write-erase cycle. Wear levelingwould ensure that such a block experienced one third as much use as ablock having its hot incremented by one per write-erase cycle.

Other schemes for managing block usage according to their block-specificaging characteristics may be implemented and techniques are not limitedto applying a fixed offset, or a multiplier to a hot count. Knowledge ofblock-by-block life expectancy may allow a wide variety of schemes tomanage block usage and avoid premature block failures which may lead topremature die failure.

FIG. 14 shows an example of a memory characterization operation. One ormore sample blocks are selected 410 and test-pattern data is programmedto the sample blocks while characterization information (such as loopcount, programming voltage, etc.) is collected 412. The data is thenmaintained in the memory cells for a period of time 413 during whichenvironmental parameters such as temperature may be controlled (e.g.high temperature applied). The test-pattern data is then read whilecollecting additional characterization information 414. In some cases,the reading may be performed periodically to check data retention overan extended period. The sample blocks are then erased while collectingadditional characterization information 416 (e.g. erase voltage, ortime, or other parameters). Memory hole diameters are then calculatedfrom the combined characterization information 418. This calculation mayprovide a memory hole profile that is an aggregate for the block, or maycalculate a single memory hole diameter that is aggregated over theblock (average, weighted average, or some other aggregated value). Whileprogramming, data retention, reading, and erasing are all performed inthis example, characterization may be based on just one or two suchoperations (e.g. program and erase, without read) in some cases.Calculated memory hole diameters may then be used for a variety ofpurposes.

Memory characterization may be performed prior to use (at the factory orduring initialization). Memory characterization may also be performedafter some significant use. While the physical dimensions of a memoryhole, or memory hole structure, may remain the same, somecharacterization information may change and may provide insight into howmemory cells change with use. Such information may allow readjustment ofoperating parameters from their initial settings. Portions of the memoryarray that are wearing out faster may also be identified in this way andcorrective action may be taken (e.g. hot counts may be adjusted toreflect any areas that appear to be in danger of wearing outprematurely).

FIG. 15 shows an example of hardware that may be used to implementaspects of the present invention. A memory system 520, which may beimplemented in a memory card, USB drive, Solid State Drive (SSD) orother unit, contains a memory controller 522 and a memory IntegratedCircuit (IC) 524. The memory IC includes a three dimensional NAND array526 in which memory hole structures extend vertically to connect memorycells at different levels along NAND strings. The memory IC 524 alsoincludes peripheral circuits 528 including a write circuit 530. Thewrite circuit 530 may be configured to write sample data to sample wordlines at different levels of 3-D NAND array 526. A characterizationcircuit 532 is also provided to receive characterization information andto determine one or more physical dimensions of memory hole structuresat different levels (e.g. memory hole diameter at different levels). Aread circuit 534 is provided to read sample data and send informationregarding the reading to the characterization circuit. An erase circuit536 is provided to erase blocks and send information regarding the eraseto the characterization circuit.

CONCLUSION

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application, tothereby enable others skilled in the art to best utilize the inventionin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

It is claimed:
 1. A method of characterizing a three-dimensional NANDmemory die comprising: selecting a plurality of sample blocks from thethree-dimensional NAND memory array; writing sample data to a pluralityof sample word lines of a plurality of physical levels of the sampleblocks to obtain characterization information for the sample word lines;and calculating a physical dimension of memory cells at each of theplurality of levels from the characterization information.
 2. The methodof claim 1 wherein the sample data consists of a predetermined testpattern for efficiently obtaining the characterization information. 3.The method of claim 2 wherein the test pattern assigns first logicstates to memory cells on a drain side of a NAND string and assignssecond logic states that are the inverse of the corresponding firstlogic states to corresponding memory cells on the source side of theNAND string.
 4. The method of claim 1 wherein the physical dimension isa diameter of a vertical memory hole that extends through memory cellsin each of the plurality of levels.
 5. The method of claim 1 wherein thephysical dimension is a thickness of a layer formed in a memory holethat extends through memory cells in each of the plurality of levels. 6.The method of claim 1 wherein the three-dimensional NAND memory diecomprises a plurality of planes, and wherein selecting the plurality ofsample blocks comprises selecting at least one sample block from each ofthe plurality of planes.
 7. The method of claim 1 wherein the pluralityof sample word lines of the plurality of physical levels includes atleast one word line from each level in the three-dimensional NAND memorydie.
 8. The method of claim 1 wherein the plurality of sample word linescomprises all word lines of a sample block.
 9. The method of claim 1further comprising recording the physical dimension in thethree-dimensional NAND memory die.
 10. The method of claim 1 furthercomprising selecting operating parameters for memory cells at each ofthe plurality of levels based on the calculated physical dimension ofmemory cells at each of the plurality of levels.
 11. The method of claim10 wherein the operating parameters include programming voltage and/orprogramming time used during a write operation.
 12. The method of claim10 further comprising recording the selected operating parameters foreach of the plurality of levels.
 13. The method of claim 10 furthercomprising selecting parameter updating schemes for the selectedoperating parameters based on the calculated physical dimension of thememory cells at each of the plurality of levels.
 14. The method of claim13 wherein a first parameter updating scheme updates parametersassociated with small memory hole diameter at a first rate and a secondparameter updating scheme updates parameters associated with largememory hole diameter at a second rate that is different to the firstrate.
 15. The method of claim 14 wherein the first parameter updatingscheme updates a wear level indicator associated with small memory holediameter at the first rate and the second parameter updating schemeupdates a wear level indicator associated with large memory holediameter at a second rate that is slower than the first rate.
 16. Amethod of characterizing a three-dimensional NAND memory die comprising:selecting a plurality of sample blocks from the three-dimensional NANDmemory array; writing sample data to a plurality of sample word lines ina sample block, each physical level in a sample block containing atleast one of the plurality of sample word lines, to obtaincharacterization information for the sample word lines; and calculatinga memory hole diameter at each physical level in the sample block fromthe characterization information.
 17. The method of claim 16 wherein thewrite characterization information includes loop count information forprogramming the sample word lines.
 18. The method of claim 16 whereinthe write characterization information includes information obtainedfrom verification when programming the sample word lines.
 19. The methodof claim 16 wherein the write characterization information includesmaximum programming voltage information for programming the sample wordlines.
 20. The method of claim 16 further comprising calculating a wearrate for each level from the calculated memory hole diameter for thelevel.
 21. The method of claim 20 wherein a wear rate for a particularlevel indicates the rate at which memory cells of the level approach awear-out condition with increasing numbers of write-erase cycles.
 22. Athree-dimensional NAND memory comprising: an array of memory cellsarranged in a plurality of levels; a plurality of memory hole structuresextending vertically through the plurality of levels to connect memorycells of the plurality of levels in NAND strings; a write circuitconfigured to write sample data to sample word lines at different levelsof the plurality of levels; and a characterization circuit configured toreceive information regarding the writing of sample data to sample wordlines from the write circuit, the characterization circuit determiningone or more physical dimensions of a memory hole structure at thedifferent levels from the information.
 23. The three-dimensional NANDmemory of claim 22 further comprising read circuits configured to readthe sample data from the sample word lines at different levels of theplurality of levels and to send information regarding the reading ofsample data to the characterization circuit.
 24. The three-dimensionalNAND memory of claim 23 wherein the information regarding the reading ofsample data is used to determine the one or more physical dimensions.25. The three-dimensional NAND memory of claim 22 wherein the one ormore physical dimensions includes an outer dimension of the memory holestructure established by an inner dimension of a memory hole in whichthe memory hole structure is formed.
 26. The three-dimensional NANDmemory of claim 15 wherein the information regarding the writing ofsample data to sample word lines includes at least one of: loop countinformation, verification information, and maximum programming voltageinformation for each of the sample word lines.
 27. A method of operatinga three-dimensional NAND memory die comprising: testing memory cells ata plurality of levels in the three-dimensional NAND memory array toobtain characterization information for each of the plurality of levels;calculating a physical dimension of memory cells at each of theplurality of levels from the characterization information; calculatingat least one initial value of an operating parameter for each of theplurality of levels, the initial value of the operating parameter for alevel calculated from the physical dimension calculated for the level;and calculating a rate of change of the operating parameter for each ofthe plurality of levels, the rate of change of the operating parameterfor a level calculated from the physical dimension calculated for thelevel.
 28. The method of claim 27 wherein the physical dimension is adiameter of a memory hole that extends through memory cells.
 29. Themethod of claim 28 wherein a higher rate of change of the operatingparameter is calculated for smaller memory hole diameter and a lowerrate of change of the operating parameter is calculated for largermemory hole diameter.
 30. The method of claim 27 further comprising,after a period of use, repeating testing of the memory cells at theplurality of levels in the three-dimensional NAND memory array to obtainpost-use characterization information.
 31. The method of claim 30further comprising comparing the post-use characterization informationwith the characterization information and recalculating the physicaldimension of memory cells at each of the plurality of levels from thepost-use characterization information if a difference between the postuse characterization information and the characterization informationexceeds a threshold amount.
 32. The method of claim 28 furthercomprising calculating an aggregated memory hole diameter for a blockand calculating a wear rate for the block from the aggregated memoryhole diameter.
 33. The method of claim 32 further comprising calculatingan effective age for the block from the number of write-erase cyclesexperienced by the block and the wear rate calculated for the block.